Well you shouldn't have been surprised as it's not anything I've not said many times before.

Well sticking with the digital->DAC bit for the moment (which is what this thread is about after all)...that's certainly one approach. Seems much better to me to make the DAC clock insensitive to any of the upstream interference. Obvious approaches are either:

a) smooth out variations in the input clock (shades of DAC64) -extract clock from least data-sensitive part of data stream, i.e. frame sync bits + PLL + FIFO with enough buffer memory to accommodate maximum possible deviation from nominal - depends on TC of the PLL. Not sure of the parts cost of this, doubt it's high, could possibly check with our electronics engineer if necessary. (Ah, he just phoned me anyway...logic could probably all fit in one smallish FPGA, cost probably £100 max, £50 in volume).

b) make data stream demand led (i.e. sync/clock-link type solution)

(Opto-isolation may be helpful if any residual noise is a problem)

Nothing I have any experience of...so that's for others to say. Maybe it's in those papers dat19 refererred to...so it would be nice to see what they say. (There's also some simplified stuff..not sure how helpful...in that Altman link, although I've not read it all.