Hi,
rsand said:
So does this dac ignore the clockin your transport and re clock?
Not quiet. There are four general options for DAC Side Reclocking of the Data to the DAC WITHOUT letting the DAC actually clock the Transport.
1) Secondary PLL
(PLL = PhaseLockedLoop a way to syncronise a given clock like 12.228MHz for digital audio with a lower rate clock like the S/P-DIF frame-clock)
Every PLL will have a cutoff frequency, below this frequency any change in input frequency (jitter) is passed on, chages with a higher frequency will be progressively suppressed as the frequency goes up. Funnily enough, Multibit DAC are really only sensitive to audio band and slightly above jitter, any jitter above the sample rate is suppressed anyway.
Most receivers PLL cannot reject jitter in the audio band (Cirrus Logic Parts suppress jitter above 10KHz with a slow falling slope, meaning at 44KHz there virtually no jitter attenuation) as it is required to lock onto a 44.1 or even 96KHz datastream which requires a quick response.
A secondary PLL can have a much slower response with a lower corner. Such a PLL can be analogue or digital. The kind of syncronous memory buffer as used by Lavry is actually a digital PLL, an analogue version is used in the earlier Audio Synthesis DAX.
A slight modification of this is a scheme I call 2-Speed PLL, where the original PLL in the receiver is slowed down severely once lock has been achieved so that the corner frequency is very low. I am still working very slowly on that, for DIY it would likely take just a few parts and could be fitted to any CS8412/14 et al equipped DAC. Maybe more another time, but corner frequencies for the PLL in the 10Hz region are possible.
2) Asyncronous output clock
Some receivers like various Cirrus Logic Parts (and possibly the DIR1703 from BB) support certain modes where an external clock is used to clock the data out of the receiver. The assumption is that the application circuit will take care of adjusting either the input or output clock to match.
If a free running oscillator is used (DDDAC1543 and the StormDigital DAC discussed elsewhere use this) there is no syncronicity and if both clocks differ enough in frequency the system will either drop or repeat a single sample in an interval determined by the difference between the clock frequencies (the larger the clock difference the more frequent the dropped or repeated samples).
In such an application it would be wise to fit identical clock generators with a very narrow specified frequency tolerance (2 - 5 ppm) to both DAC and Transport (making it strictly a DIY solution), a single frame will be dropped/repeated only every few seconds or so, which should be completely irrelevant.
If the difference is large (as much as 5000ppm from nominal have been recorded with cheap players which would cause a dropped/repeated frame every 25mS appx. if my math is on the money) there may very well be audible problems.
The above would seem best for DIY use, if you can live with a single sample rate and modify the transport. I suspect one could use the various frequency status pins to select a range of clocks for the output but the whole thing becomes VERY messy.
3) Memory Buffer and free-running output clock
This is really a variation of 2), except here we do not just buffer a single sample, but a large number of samples, so that we do not get dropped/repeated samples at all if the buffer is large enough.
Chord seemingly uses this principle, but it is all a question (again) of how much difference between the clocks you want to allow and you need buffer as much as the possible lost samples and have twice that amount of memory.
Morgan Jones worked out that around 16 - 32MB would be needed IIRC, this was long ago.
4) Asyncronous Reclocking
This is actually an interresting one, it has been first (AFAIK) introduced by Kusonoki San, it has since gained a lot of popularity. What it does is to use a free-running oscillator with a frequency not at all related to the sample frequency and use that to reclock the critical (latch enable) clock. The "Monica/Monica2" uses this principle, as do many others.
As a result jitter is actually NOT AT ALL reduced, instead it is shifted in terms of level (peak-peak jitter becomes invariably a constant, namely the clock cycle of the re-clocking clock) and the entire jitter spectrum is shifted, by producing in effect a beat-frequency effect between the two clocks.
The resulting interactions are unpredictable and it is obvious that selecting the highest practical clock frequency (how about 125MHz - this BTW gives still 8nS or 8000pS peak-peak jitter). I suspect the principle is similar to what Altman Micro uses in the Jisco/PCI products, but I cannot be sure.
' '
So, what is the bottom line? Unless you use a secondary PLL you are invariably inviting a number of problems. The audibility of these depends on a number of factor and may be from "non at all" to "bad".
rsand said:
Tempted (for the price) to build one and fit it inside the copland rather than outboard. Could I use the power supply from the copland internal dac to power this?
If you fit a seperate DAC internal you are better off tapping the actual I2S signal on the Coplands PCB, prior to the Digital Filter and using that. Much lower jitter, easy re-clocking from the clock source in the Copland etc.
If you can use the existing supply depends on the supply specification, if there is enough spare capacity and the correct voltages available this may very well be a good option.
Ciao T
